(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of conductive wiring and conductive vias on a semiconductor substrate, and to a dual damascene CMP (Chemical Mechanical Polishing) process for forming a planarized conductive interconnection structure.
(2) Description of the Related Art
Due to shrinkage in size of semiconductor components and increased circuit density the need arises to obtain contacts having surfaces of very small area and spaced at very small intervals. Furthermore, the complexity of interconnecting the many components in the dense circuits requires multiple layers of interconnecting conductor lines. As contact size has diminished to 0.5 micron or less, traditional methods for forming interconnection structures are not successful. One such traditional method involves deposition of a conductive layer onto an insulation layer, followed by lithography and subtractive etching of the conductive layer to form an interconnection pattern. After deposition of another insulation layer, via holes are formed at selected sites and filled with conductive material to make contact to the interconnection pattern. Then the above process is repeated to form multiple interconnection levels.
Recently damascene processes have been used as a replacement for the traditional deposition and subtractive etch processes. Damascene basically involves the formation of a trench which is filled in with a metal. Damascene differs from the traditional deposition and subtractive etch processes of providing an interconnection pattern, by providing a trench which is filled in with metal followed by planarization, whereas the traditional deposition and subtractive etch process involves forming a metal wiring interconnection pattern and then filling in the interwiring spaces with a dielectric material.
In a single damascene process the conductive plugs and each interconnection wiring pattern level are formed independently. Thus to form multiple wiring levels numerous processing steps are required. Furthermore, undesirable interfaces exist between each conductive plug and each interconnection wiring pattern.
An improvement to the single damascene process is the dual damascene process, illustrated in FIGS. 1A to 1C. In the dual damascene process a first insulative layer 12 is deposited on a semiconductor substrate 11, and an etch stop layer 13 is deposited on the first insulative layer 12. Then a second insulative layer 14 is deposited on the etch stop layer 13. Typically, the first insulative layer 12 and the second insulative layer 14 are silicon oxide and the etch stop layer 13 is silicon nitride. As shown in FIG. 1A, a first photoresist mask 15 is formed on the second insulative layer and then a first opening is formed in the second insulative layer 14, but not penetrating etch stop layer 13. RIE (Reactive Ion Etching) is used to form the first opening in the second insulative layer and results in vertical side walls for the opening. As shown in FIG. 1B, after removing the first photoresist mask 15, a second photoresist mask 16 is formed on the second insulative layer 14. Then a trench is etched into the second insulative layer 14, while simultaneously extending the first opening through the etch stop layer 13 and the first insulative layer 12. Again RIE is used to etch the trench and extend the first opening, resulting in vertical sidewalls for the trench and the opening. As shown in FIG. 1C, after removal of the second photoresist mask 16, a conductive layer 17 is deposited to simultaneously fill the via and trench with conductive material.
As contact size becomes smaller, practice of the conventional dual damascene process illustrated in FIGS. 1A to 1C, results in imperfections in filling the opening and trench with conductive material. The principle problem is the inability to completely fill features that have high aspect ratios. Aspect ratio is defined as the ratio of the depth of the feature to the width of the feature. When the aspect ratio for a feature becomes larger than about 2, filling is incomplete and voids are formed within the conductive material. Such voids result in yield loss for the fabrication process or degraded current carrying capacity for the conductor.
Therefore, an important challenge in the dual damascene process is to achieve a trench and contact cross-sectional profile that is more easily filled with deposited conductive material while maintaining small contact size and without adding costly processing steps.
U.S. Pat. No. 4,349,584 entitled "Process For Tapering Openings In Ternary Glass Coatings" granted Sep. 14, 1982 to Doris W. Flatley et al describes a process for tapering openings in glass coatings formed from a layer of dense, undoped silicon oxide and a layer of ternary doped silicon oxide. After the contact openings are formed, both oxide layers are heated to a temperature below the flow temperature of the doped layer for a period of time sufficient to only soften and partially reflow the doped layer.
U.S. Pat. No. 5,595,937 entitled "Method For Fabricating Semiconductor Device With Interconnections Buried In Trenches" granted Jan. 21, 1997 to Kaoru Mikagi shows a method of forming interconnections buried in trenches.
U.S. Pat. No. 5,614,765 entitled "Self Aligned Via Dual Damascene" granted Mar. 25, 1997 to Steven Avanzino et al describes a process for forming both the conductive lines and conductive vias with only a single pattern exposure step for the openings for both the lines and the vias, thereby eliminating the critical alignment of two masks.
U.S. Pat. No. 5,635,423 entitled "Simplified Dual Damascene Process For Multi-Level Metallization And Interconnection Structure" granted Jun. 3, 1997 to Richard J. Huang et al describes a process for forming conductive lines and conductive vias in a structure comprising a first insulation layer, an etch stop layer, and a second insulation layer.
U.S. Pat. No. 5,424,247 entitled "Method For Making Contact Holes In Semiconductor Devices" granted Jun. 13, 1995 to Natsuki Sato teaches a method for forming a tapered opening using a reflow process.
The present invention is directed to a novel method of formation of conductive wiring and conductive contact holes on a semiconductor substrate, and to a dual damascene CMP (Chemical Mechanical Polishing) process for forming a planarized conductive interconnection structure.